1. Field of the Invention
This invention is related to the field of scan testing of integrated circuits.
2. Description of the Related Art
Over time, larger numbers of transistors have been integrated into integrated circuits. As more transistors can be integrated, the functionality that can be realized in a given integrated circuit increases. The complexity of the integrated circuit similarly increases, and thus the ability to test the circuitry to ensure that it is functioning properly remains an important issue.
One mechanism used to test integrated circuits is scan testing (or, more briefly, “scan”). To support scan testing, various state elements (e.g. flops, latches, registers, etc.) are typically coupled together in a “scan chain”. The state elements may include separate scan-in inputs and/or scan-out outputs which may be connected together to form a scan chain. Alternatively, additional circuitry may mux the scan-in and functional inputs to the input of the state element and the output of the state element may be used for both scan values and functional values. Scan data is shifted into the scan chain, thus loading the state elements with a desired set of test data. The circuitry may be clocked functionally for one or more clock cycles, and then the result data may be shifted out of the scan chain. The result data may be compared to expected data to detect defects or improper operation.
Implementing scan circuitry in an integrated circuit includes a certain amount of overhead, and so in many cases a design decision is made as to how many of the state elements are scannable (e.g. how many state elements include corresponding scan circuitry). If state elements are implemented without scan circuitry, the test coverage that can be achieved using scan is reduced.
The overhead can be manifest in several ways. For example, the area occupied by the scan circuitry may be relatively large. In one prior art method, the scan chain is implemented as a separate set of master/slave latches (clocked by separate master and slave scan clocks). Once the scan data is scanned into the scan chain, the scan data may be loaded in parallel into the corresponding state elements.
In some cases, the overhead may include additional load presented on state elements and related circuitry by the scan circuitry. The additional load can slow down the functional (non-scan) circuitry, reducing the cycle times achievable in the integrated circuit. In low power designs (in which reducing power consumption of the integrated circuit is considered a priority), the power consumed by the scan circuitry (even when scan is not active) may also be considered overhead.